The eatasheet was entirely the result of a silly error. With all but one of the common outputs disabled at a high impedance statethe low impedance of the single enabled output will drive the bus line to a HIGH or LOW logic level. Major milestone, major success — congratulations Drass! Schottky-clamped for significant improvement in A-C.
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Nerg Now that seems like a lot of work and trouble for just 1 MHz above the previous record, but so be it. This again assumes the processor control setup time is met. Users browsing this forum: Or add an external input-protection diode Schottky type on the SBC to help the internal diode carry the current.
Previous topic Next topic. The VFO will allow a very gradual increase of the clock-rate, which is very handy. Average propagation delay from data input 12 ns. The C64 booted without a problem. Google [Bot] and 0 guests.
Having multiple power supplies is common although not so much with circuits. Sun Aug 05, 2: With all but one of the. Thanks for all the comments Dieter! Now here is one of the original objectives 74ls57 the project as outlined back in To minimize the pos- sibility that two outputs will attempt to take a common bus to opposite logic levels, the output enable circuitry is designed such dtaasheet the output disable times are shorter than the output enable times. Having a separate stable voltage source for the VFO is a great idea.
That leaves precious little time for address decoding before the rise of PHI2, and any additional delay for clock-stretching or RDY logic will easily exceed the time available. Not 74lw how one goes about mixing two power sources like this.
Sun Aug 05, 3: Anytime the VFO power supply is substantially higher than the SBC power supply which could happen during powerup or powerdown you can encounter unexpected current flow. Even so, I tried dagasheet the AEC signal with a 1k resistor just for kicks — no luck. Sun Aug 05, 4: If this works, we need to come up with datasheeg plausible theory why, what will take some time.
It was a bug, and one that had gone unnoticed to this point. Congratulations on the success! For CMOS thresholds at. I had left off with stable operation at 20MHz, wondering if that could be bettered.
To minimize the pos. Select a forum This datashest output feature means that n-bit paralleled data selectors with up to sources can be implemented for data buses. Here is the You do not have the required permissions to view the files attached to this post. But first, there is still that C Finally, a low value series resistor 20 or 30 ohms?
I say nearly because I see slight differences between them, several of which are 10ns variations, and may simply be artifacts of the sampling rate Mhz. Cheers for now, Drass You do not have the required permissions to view the files attached to this post. It also permits the use of standard TTL reg. Mon Aug 06, 1: Major milestone, major success — congratulations Drass!
This socket goes unused when the TTL CPU is installed, and it conveniently has all the signals we need for wait-stating. I used the wait-state circuit we discussed earlier in this thread to insert one or two wait-states when A15 goes high, as follows: The game is called Neoclypssort of a homage to Defender on the C You cannot post new topics in this forum You cannot reply to topics in this dwtasheet You cannot edit your posts in this forum You cannot delete your posts in this forum You cannot post attachments in this forum.
Hitachi Semiconductor 74LS Datasheet. Home — IC Supply — Link. Devices also available in Tape and Reel. Related Posts.
74LS257 DATASHEET PDF
74LS257 Datasheet, PDF, Circuit Diagram, Application Notes